IPSJ-ARC2015

Prof. Yamasaki spoke at IPSJ-ARC in Yokohama, Japan.

Nobuyuki Yamasaki, “Dependable Responsive Multithreaded Processor for Parallel/Distributed Real-Time Processing –Co-design of SoC/SiP/OS for Robot Control–,” IEICE Technical Report, Vol. 114, No. 436, ICD2014-114, pp. 21-26, Jan 2015.

CPSY2015

Mizotani, Otsuki, and Oosawa presented at IEICE SIG: Computer Systems (CPSY) in Yokohama, Japan.

Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, and Nobuyuki Yamasaki, “A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor,” IEICE Technical Report, Vol. 114, No. 427, CPSY2014-158, pp. 227-232, Jan 2015.

Shuhei Otsuki, Keigo Mizotani, Masayoshi Takasu, Daiki Yamazaki, and Nobuyuki Yamasaki, “NoC Architecture with Priority-based Packet Overtaking and Resource Control,” IEICE Technical Report, Vol. 114, No. 427, CPSY2014-126, pp. 25-30, Jan 2015.

Kohei Oosawa, Shuma Hagiwara, Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, and Nobuyuki Yamasaki, “A Latency-Aware Packet Scheduling on Responsive Link,” IEICE Technical Report, Vol. 114, No. 427, CPSY2014-159, pp. 233-238, Jan 2015.