# # The release note and change log for the RMTP Cross BINUTILS # ### 2 August, 2006 Shinpei Kato ### BINUTILS-RMT-1.0.12 1. tc-mips.c Added the compile option "-rmtbug-syncls" and "-rmtbug-tnebj". <-rmtbug-syncls> This option inserts "sync" before the load/store instructions. This is for the bug that D bit of the cause register is possibly set when there is a load or store instruction in the target address of the branch and jump instructions. <-rmtbug-tnebj> This option inserts "tne $0 $0" before the branch and jump instructions. This is for the bug that I-MMU exception is not canceled in the case of a branch prediction miss if the exception occurs at the address fetched speculatively. ### 7 July, 2006 Shinpei Kato ### BINUTILS-RMT-1.0.11 1. tc-mips.c Removed the compile option "-murmtp-xsync" and "-murmtp-lssync". Instead, added the option "-rmtbug-xsync" and "-rmtbug-lssync". Also, in order to overcome some bugs, the option "-rmtbug-delaynop", "-rmtbug-syncbj" and "-rmtbug-nopsync" are added. Here I summarize these options briefly. <-mrmtp> This option generates the code for RMTP. <-murmtp> This option generates the code for u-RMTP. <-rmtbug-lssync> This option inserts "sync" instruction after the load/store instruction in the case that the branch instruction follows within three instructions. This is for the bug that the store instruction would be flushed and not write to the memory if the store instruction and the branch instruction which missed the prediction are commited at the same clock. <-rmtbug-xsync> This option inserts "sync" instruction, in order to avoid breaking the registers, after the instructions which might cause an exception. When you specify this option, it is obvious that you don't have to specify "-rmtbug-lssync" option. <-rmtbug-delaynop> This option tells the compiler to put "nop" or "rmtnop" instruction in the delay slot. This is for the bug that "eret" returns the branch destination address if some exception occurs at the delay slot. For example, consider the following code. bne $8, $9, <0xXXXXXXXX> sw $10, 0x10($11) If "sw" occurs the TLB entry miss exception, this "sw" should be executed after coming back from the exception, but "eret" returns <0xXXXXXXXX> due to the bug. <-rmtbug-syncbj> This option inserts "sync" instruction before branch/jump instructions. This is for the bug that the MMU exception occurs at the destination address of "jal" instruction in the case that this "jal" instruction follows after the conditional branch instruction even if the condition of the branch is not satisfied. <-rmtbug-nopsync> This option swaps all the "nop" and "rmtnop" instructions to "sync" instruction. This is for the bug that there are some problems in epc_data (this register cannot be observed from software) in the case that the I-MMU exception occurs. These options can be combined together. For example, you can specify as follows. % mips-rmt-elf-gcc -Wa,-murmtp \ -Wa,-rmtbug-xsync \ -Wa,-rmtbug-syncbj \ -Wa,-rmtbug-delaynop \ -Wa,-rmtbug-nopsync ### 5 June, 2006 Shinpei Kato ### BINUTILS-RMT-1.0.10 1. tc-mips.c Added the "-murmtp-xsync" option. This option inserts the "sync" instruction after the instructions which might cause some exception, in order to avoid breaking the registers. ### 25 May, 2006 Shinpei Kato ### BINUTILS-RMT-1.0.9 1. tc-mips.c Added the "-murmtp-lssync" option. This option always inserts the "sync" instruction after the load/store instruction. 2. mips-opc.c Added the following instructions. mfimm3 rd,rs,rt mfdmm3 rd,rs,rt ### 3 Mar, 2006 Shinpei Kato ### BINUTILS-RMT-1.0.8 1. tc-mips.c Changed so that all the nop instructions are replaced with the "rmtnop" instruction ### 28 Dec, 2005 Shinpei Kato ### BINUTILS-RMT-1.0.7 1. tc-mips.c Enabled to specify the options; "-murmtp" and "-mrmtp". The option "-mrmtp" inserts serveral "rmtnop" instructions so as to avoid the bug that it does not jump to a proper address if there are multiple branch instructions in the same cache line and the branch prediction of the first branch instruction is missed. This option also inserts "sync" instruction so as to avoid the bug that a store instruction does not work properly if there is a conditional branch instruction before the store instruction and the branch prediction failed. The option "-murmtp" deals with only the latter bug. ### 3 Mar, 2005 Shinpei Kato ### BINUTILS-RMT-1.0.6 1. mips-opc.c Fixed the opecode of iolb ### 9 Feb, 2005 Shinpei Kato ### BINUTILS-RMT-1.0.5 1. mips-opc.c Fixed the opecode of vmac.* and the operands of vfrsl.* ### 4 Feb, 2005 Shinpei Kato ### BINUTILS-RMT-1.0.4 1. mips-opc.c Fixed the operands of vliw, visw, vflw, vfld, vfsw, vfsd 2. tc-mips.c Inserted wrong path detector ### 2 Feb, 2005 Shinpei Kato ### BINUTILS-RMT-1.0.3 1. mips-opc.c Fixed misprinting of the vilw mnemonic 2. mips-opc.c Fixed the opecode of vacc instruction ### 20 Jan, 2005 Shinpei Kato ### BINUTILS-RMT-1.0.2 1. mips-opc.c Fixed gpco, gppr, fpco, fppr instructions. 2. tc-mips.c Enabled 5-bit thread id register and shared register. ### 25 Dec, 2004 Shinpei Kato ### BINUTILS-RMT-1.0.1 1. mips-opc.c Fixed all the SIMD instructions since the specification changed ### 17 Oct, 2004 Shinpei Kato ### BINUTILS-RMT-1.0.0 1. Released the cross binutils for RMT processor. - Being based on MIPS version - Most of the rmt instructions are available - Only the instructions with special format are not available - Able to switch to the version of rmtnop