CATA2015

Dr. Chishiro, Mizotani, Takasu, and Kumura presented at the 30th International Conference on Computers and Their Applications (CATA2015) in Hawaii, USA.

Hiroyuki Chishiro and Nobuyuki Yamasaki, “Zero-Jitter Technique for Semi-Fixed-Priority Scheduling with Harmonic Periodic Task Sets,” In Proceedings of the 30th International Conference on Computers and Their Applications, March 2015.

Keigo Mizotani, Yusuke Hatori, Masayoshi Takasu, Yusuke Kumura, Hiroyuki Chishiro, and Nobuyuki Yamasaki, “An Integration of Imprecise Computation Model and Real-Time Voltage and Frequency Scaling,” In Proceedings of the 30th International Conference on Computers and Their Applications, March 2015.

Masayoshi Takasu, Keigo Mizotani, Yusuke Kumura, Hiroyuki Chishiro, and Nobuyuki Yamasaki, “Leakage-Aware Partitioning of Real-Time Tasks for Multiprocessor Systems,” In Proceedings of the 30th International Conference on Computers and Their Applications, March 2015.

Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, Hiroyuki Chishiro, and Nobuyuki Yamasaki, “Overhead-Aware Schedulability Analysis on 8-way SMT Processor,” In Proceedings of the 30th International Conference on Computers and Their Applications, March 2015.

ETNET2015

Murata, Matsui, and Yamada presented at CPSY/IPSJ-EMB/IPSJ-SLDM/DC in Amami, Japan.

Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, and Nobuyuki Yamasaki, “A Resource Utilization Aware Method to Improve Throughput on RMT Processor,” IEICE Technical Report, Mar 2015.

Tsukasa Matsui, Shuma Matsui, Keigo Mizotani, and Nobuyuki Yamasaki, “Adaptive Error Correcting Code by Priority on RMT Processor,” IEICE Technical Report, Mar 2015.

Kenji Yamada, Yusuke Hatori, Shuma Hagiwara, Keigo Mizotani, Masayoshi Takasu, and Nobuyuki Yamasaki, “Real-Time Static Voltage and Frequency Scaling on RMT Processor using Instructions Per Clock Cycle Control,” IEICE Technical Report, Mar 2015.

IPSJ-ARC2015

Prof. Yamasaki spoke at IPSJ-ARC in Yokohama, Japan.

Nobuyuki Yamasaki, “Dependable Responsive Multithreaded Processor for Parallel/Distributed Real-Time Processing –Co-design of SoC/SiP/OS for Robot Control–,” IEICE Technical Report, Vol. 114, No. 436, ICD2014-114, pp. 21-26, Jan 2015.

CPSY2015

Mizotani, Otsuki, and Oosawa presented at IEICE SIG: Computer Systems (CPSY) in Yokohama, Japan.

Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, and Nobuyuki Yamasaki, “A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor,” IEICE Technical Report, Vol. 114, No. 427, CPSY2014-158, pp. 227-232, Jan 2015.

Shuhei Otsuki, Keigo Mizotani, Masayoshi Takasu, Daiki Yamazaki, and Nobuyuki Yamasaki, “NoC Architecture with Priority-based Packet Overtaking and Resource Control,” IEICE Technical Report, Vol. 114, No. 427, CPSY2014-126, pp. 25-30, Jan 2015.

Kohei Oosawa, Shuma Hagiwara, Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, and Nobuyuki Yamasaki, “A Latency-Aware Packet Scheduling on Responsive Link,” IEICE Technical Report, Vol. 114, No. 427, CPSY2014-159, pp. 233-238, Jan 2015.

IPSJ Journal 2014

Mizotani’s paper has been accepted to Information Processing Society of Japan (IPSJ) Journal Embedded Systems Engineering Special Edition Vol.55 No.8.

Keigo Mizotani, Rikuhei Ueda, Masayoshi Takasu, Hiroyuki Chishiro, Hiroki Matsutani, and Nobuyuki Yamasaki, “Experimental Evaluation of Temperature-Aware DVFS on Imprecise Computation Model”, Information Processing Society of Japan (IPSJ) Journal Embedded Systems Engineering Special Edition, Vol.55, No.8, pp.1841-1855, Aug. 2014.